1. Field of the Invention
Embodiments of the invention relate generally to a nonvolatile semiconductor memory devices. More particularly, embodiments of the invention relate to a level shifter adapted to shift a swing voltage and a block driver including same.
This application claims priority to Korean Patent Application No. 10-2005-117840 filed Dec. 6, 2005, the subject matter of which is hereby incorporated by reference.
2. Description of the Related Art
Nonvolatile semiconductor memory devices include a plurality of memory cells adapted to store data. During a data programming operation, a high-level program voltage (e.g., 23.5 V) is provided to the word line of a selected memory cell. To accomplish the programming operation, however, a transmission transistor adapted to transmit the program voltage must be gated by a block word signal. The block word signal is typically a shifted or boosted voltage signal (e.g., 25 V). Thus, the block word voltage is higher than the program voltage.
In this regard, the block word signal is activated in response to a decoding signal adapted to select a memory block including the memory cell to be programmed. A power supply voltage is typically used as a pull-up voltage for the decoding signal. Therefore, in order to generate the block word signal using a pull-up voltage to generate a boosted voltage, a level shifter circuit is generally embedded within a block driver adapted to generate the block word signal.
FIG. 1 is a circuit diagram illustrating a level shifter embedded in a conventional block driver. In the level shifter of FIG. 1, when a decoding signal /XDEC is driven to a ground voltage VSS, a block word signal BLKWL is enabled to a boost voltage VPP through an NMOS transistor 13 and a PMOS transistor 15. Furthermore, when the decoding signal /XDEC is driven to a power supply voltage VDD, the block word signal BLKWL is disabled to a ground voltage VSS by a disable unit 11.
NMOS transistor 13 is typically a depletion-type transistor. Therefore, even if a voltage close to a ground voltage VSS is applied to NMOS transistor 13, a predetermined amount of current flows. As a result, PMOS transistor 15 must be designed with a high threshold voltage when an output signal VOUT is disabled. Since PMOS transistor 15 has a high threshold voltage, it minimizes leakage current between the boost voltage VPP and the block word signal BLKWL.
However, in the level shifter of FIG. 1, a common junction terminal N14 between depletion-type NMOS transistor 13 and PMOS transistor 15 is connected to the bulk of PMOS transistor 15. That is, the threshold voltage Vtn1 (e.g., 2.5 V) of depletion-type NMOS transistor 13 is applied to the bulk of PMOS transistor 15 when the output signal VOUT is disabled. In this case, the threshold voltage Vtp of PMOS transistor 15 is about −0.7 V. For reference, when the block word signal BLKWL is enabled to a boost voltage VPP, the boost voltage VPP is applied to the bulk of PMOS transistor 15.
As a result, PMOS transistor 15 of FIG. 1 has a relatively low threshold voltage, so that relatively high sub-threshold current is generated. Particularly, when the level of a power supply voltage VDD, that is, the operating voltage of a nonvolatile semiconductor memory device incorporating the lever shifter circuit, decreases to about 1.8 V, PMOS transistor 15 of FIG. 1 is turned ON, so that current I1 passing through depletion NMOS transistor 13 and PMOS transistor 15 increases considerably.
Accordingly, conventional level shifters, such the one illustrated above, and block driver circuits including such conventional level shifters have a problem with high levels of leakage current. Excessive leakage current is particularly undesirable in many contemporary running off battery power sources, such as cell phones, laptop computers, PDAs, etc.